1. Field of the Invention
The present invention relates to a data processing device (microprocessing unit), more particularly, to an address monitoring device in a data processing device including a cache memory.
2. Description of the Related Art
Conventionally, in a general address monitoring device, an address (write address) and a write instruction signal are monitored, and when the write address coincides with an address stored in a tag memory, data stored in the tag memory are invalidated.
Recently, in a data processing system having a plurality of microprocessing units or a direct memory access controller, a block transfer process for transferring data is carried out. Note, if the same address data as that written into the cache memory in the microprocessing unit is rewritten being transferred by the direct memory access controller, if the contents of the cache are not invalidated or rewritten, the data written in the cache memory in the microprocessing unit is inconsistent with the data in the main memory. This inconsistency between the main memory and the cache memory must be prevented even when the data are transferred by using a block transfer process.